1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor devices. More specifically, the invention relates to the fabrication of bipolar transistors.
2. Background Art
As modern electronic devices increase in speed while decreasing in size and price, semiconductor manufacturers are challenged to provide low-cost, high speed, and small size transistors for these devices. To meet this challenge, semiconductor manufacturers must accurately control the size of certain features that critically affect the performance of transistors on a semiconductor wafer, such as emitter widths of bipolar transistors. Furthermore, various parts of the bipolar transistor must be properly aligned to ensure that the bipolar transistor meets performance requirements. For example, the emitter and the extrinsic base implant in a heterojunction bipolar transistor (HBT) must be properly aligned to prevent an undesirable increase in base resistance. Furthermore, to reduce costs, semiconductor manufacturers are challenged to meet desired bipolar transistor performance requirements while fabricating bipolar transistors having increased manufacturability.
In one conventional fabrication process for a bipolar transistor, such as an HBT, semiconductor manufacturers utilize a first photomask to control the bipolar transistor's emitter width, which is generally referred to as a critical dimension, or “CD.” A second photomask, which must be properly aligned with the first photomask, is utilized to determine the boundaries of the heavily doped extrinsic base regions of the bipolar transistor. Misalignment of the two photomasks causes, among other things, the distance across the link base region of the bipolar transistor, i.e. the region between the base-emitter junction and the extrinsic base region, to vary in an unpredictable fashion. Because there is always a margin of error in the alignment of the two photomasks, the distance across the link base region must be increased to account for the misalignment. This results, for example, in an undesirable increase in base resistance. Additionally, in the two-photomask fabrication process described above, the first photomask must be accurately controlled to control the emitter width of the bipolar transistor. Also, misalignment of the two photomasks can cause an undesirable reduction in manufacturing yield, which can cause a corresponding increase in manufacturing cost.
Other fabrication processes and tools have been tried in attempts to solve the problem of aligning the link base and extrinsic base to the emitter in bipolar transistor devices. One approach requires the use of selective epitaxy along with the use of an inside spacer. Selective epitaxy presents a problem in that it is not currently used in high volume production of semiconductor devices. Selective epitaxy presents another problem in that selective epitaxial deposition occurs only on silicon regions and not on oxide regions. Since most process monitoring is done on oxide regions, selective epitaxy results in a substantial loss of process monitoring capability. Use of an inside spacer presents a further problem in that variability of emitter width is greater than with other methods, so some accuracy in control of emitter width is lost.
Additionally, current leakage between the emitter, typically made of polycrystalline silicon (“poly”), and the base regions situated underneath the emitter poly is affected by the thickness of an oxide layer situated between the emitter poly and base regions of the bipolar transistor. The thickness of the oxide layer situated between emitter poly and base regions of the bipolar transistor is undesirably decreased by, for example, erosion caused by a wet etch utilized in an emitter pre-clean process, which can result in increased current leakage between the emitter poly and the base regions. As a result, the performance and manufacturability of the bipolar transistor can be undesirably decreased.
Thus, there is need in the art for an effectively fabricated bipolar transistor.